In a semiconductor device manufacturing process, a dual damascene method is widely used to form a wiring groove or a contact hole (see, e.g., Patent Document 1).
Meanwhile, as semiconductor devices are miniaturized, a parasitic capacitance of an interlayer insulating film has become an important factor to improve wiring performance. The interlayer insulating film employs a low dielectric constant film (low-k film) made of a low-k material. Further, the low-k film is generally made of a material having end groups of alkyl groups such as methyl groups.
However, in the aforementioned conventional damascene process, the low-k film is damaged during an etching process or a resist film removing process (ashing process). This damage increases the dielectric constant of the low-k film, and decreases effects obtained by using the low-k film as the interlayer insulating film.
As a technique for recovering such damage, Patent Document 2 discloses a method for performing a silylation process after etching or removal of the resist film. The silylation process is performed to reform a damaged surface portion having end groups of OH groups by using a silylation agent such that the OH end groups can be replaced by alkyl groups such as methyl groups.
In order to apply the damage recovery process to a mass production system, it is required to check whether the apparatus is normal or not by inspecting processing conditions in a chamber set-up of the silylation processing apparatus or a daily check. Currently, in order to inspect the processing conditions, etching and ashing processes are performed on a wafer having a low-k film and a silylation process is performed thereon to prepare a sample. Then, a dilute hydrofluoric acid treatment is performed on the sample, wherein CDs or film thicknesses t are measured before and after the dilute hydrofluoric acid treatment to obtain ΔCD or Δt, thereby inspecting the processing conditions.
However, when the processing conditions are inspected by the above-described technique, the sample needs to be prepared by performing etching and ashing before the silylation process. Therefore, the sample preparation time is required and, also, the processing conditions related only to the silylation processing apparatus cannot be inspected. In other words, even if ΔCD or Δt is abnormal, it is not possible to determine whether the problem is related to the silylation process or to etching/ashing process.
Further, even if silylation conditions such as a gas concentration vary, ΔCD or Δt obtained after the dilute hydrofluoric acid treatment is hardly changed. Furthermore, even if the same ΔCD or Δt is obtained after the dilute hydrofluoric acid treatment on different samples, these samples often reveal different electrical characteristics. Namely, the processing conditions of the silylation process can not verified reliably.    [Patent Document 1] Japanese Patent Laid-open Publication No. 2002-083869    [Patent Document 2] Japanese Patent Laid-open Publication No. 2006-049798